LSIs including a flash memory continue to be miniaturized, and are entering the 65 nm era from the current 0.13 μm and 90 nm nodes era. Therefore, although the flash memory has mainly used a floating gate (FG) memory cell up to the 0.13 μm node era to meet requirements for reducing a cell area and thinning an insulation film, attention has been paid to a trap memory which uses traps discretely included in an insulating film to capture electric charges because it has been found that thinning the insulating film will be difficult in view of securement of retention property in the 90 nm node era or later. In comparison with the FG memory, the trap memory has the advantage that an effective oxide thickness can be reduced, including the reduction of a tunnel oxide film thickness, and it has a simpler device structure. The locality of an electric charge can be used to achieve a state in which two or more bits are written for one cell, and is also advantageous to reduce a cell area per one bit.
FIG. 1 is a top view of a conventional trap memory. FIGS. 2(a) and 2(b) are cross sections taken along lines A-A and B-B in FIG. 1. As illustrated in FIGS. 1 and 2, a plurality of element isolation insulating films 2 which segments an active region extends in the upper and the lower direction in FIG. 1 in a pattern of lines and spaces in the surface region of a silicon substrate 1. A laminate insulating film composed of a first gate insulating film 3, a charge accumulation layer 4 and a second gate insulating film 5 is formed over the silicon substrate 1. The predetermined number of gate conductors 6 are formed in a pattern of lines and spaces so as to be orthogonal to the active region (i.e. to be orthogonal to the element isolation insulating films 2) over the laminate insulating film. Gate side walls 7 of an insulating material are formed on the sides of the gate conductor 6. Side walls 8 of an insulating material are formed outside the gate side walls 7. The first gate insulating film 3, the charge accumulation layer 4, and the second gate insulating film 5 are patterned self-alignedly with the gate conductor 6 and the charge accumulation layer 4 does not exist outside the gate conductor 6. Hereinafter, such structured trap memory is referred to as a first conventional example.
FIG. 3 illustrates a method of producing the first example of the conventional trap memory in FIG. 1 and are cross sections taken along lines A-A in FIG. 1 according to the order of processes. As illustrated in FIG. 3(a), the first gate insulating film 3, the charge accumulation layer 4, the second gate insulating film 5 and a silicon film 6a are sequentially deposited over the silicon substrate 1 on which the element isolation insulating film (not shown) is formed. Thereafter, as illustrated in FIG. 3(b), the silicon film 6a is patterned using lithography technique and dry etching technique to form the linear gate conductor 6. The exposed first gate insulating film 3, charge accumulation layer 4 and second gate insulating film 5 are removed by etching using the patterned gate conductor 6 as a mask. As illustrated in FIG. 3(c), an insulating film is deposited and etched back to form the gate side wall 7. Then, an impurity diffusion layer 9 functioning as a source and a drain region is formed. Finally, as illustrated in FIG. 3(d), an insulating film is deposited and etched back to form the side wall 8. Thus, the first example of the conventional trap memory can be formed.
The first example of the conventional trap memory has a significant problem as described below. The problem will be described using an enlarged view of the drain end and its vicinity in FIG. 4. The trap memory performs writing such that a positive voltage is applied to the drain region (the impurity diffusion layer 9) and the gate conductor 6 to inject channel hot electrons (CHE) into the charge accumulation layer 4 near the drain end. A distribution 11 in FIG. 28 represents the distribution of electrons provided by injecting CHEs. At this point, the portion of broken line of the distribution 11 corresponding to a part of the injected electrons deviates from a charge accumulation region composed of the laminate insulating film (3, 4 and 5), so that charges are not accumulated in the charge accumulation layer 4 and escape to the electrode or the substrate. This reduces efficiency in writing the injected electrons to increase the writing time.
In the above conventional structure, a defect is generated in the insulating films at the gate end portion during the etching process for the second gate insulating film 5, the charge accumulation layer 4 and the first gate insulating film 3 illustrated in FIG. 3(b). The defect remains at the gate end portion even after the gate side wall 7 has been formed to increase a leak current through the defect and cause leakage of the accumulated charge, resulting in decrease in yield. When the gate side wall 7 is formed by the thermal oxidation of the gate conductors 6, the laminate insulating film (3, 4 and 5) at the gate end portion is simultaneously oxidized and part of the aforementioned defect is recovered. However, a bird's beak is formed on the substrate at the gate end portion by the thermal oxidation to increase the defect density of the first gate insulating film near the gate end, lowering the yield.
In order to avoid the problem of the first example of the conventional trap memory, Patent Document 1 proposes a structure in which the charge accumulation layer 4 is projected from the gate conductors 6. FIG. 5 is a top view of the trap memory disclosed in Patent Document 1. FIGS. 6(a) and 6(b) are cross sections taken along lines A-A and B-B in FIG. 5. In FIGS. 5 and 6, the same portions as those in the first example illustrated in FIGS. 1 and 2 are denoted by the same reference numerals and the duplicated description is omitted. In the present conventional example, the laminate insulating film (3 to 5) including the charge accumulation layer 4 is projected from the end of the gate conductors 6. Hereinafter, this structure is referred to as a second conventional example.
A method of producing the second example of the conventional trap memory is described below with reference to FIG. 7. FIG. 7 are cross sections illustrating the method of producing the second conventional example according to the order of processes. As illustrated in FIG. 7(a), the first gate insulating film 3, the charge accumulation layer 4, the second gate insulating film 5 and a silicon film 6a for forming a gate electrode are sequentially deposited over the silicon substrate 1. As illustrated in FIG. 7(b), the silicon film 6a is patterned using dry etching technique to form the gate conductor 6. At this point, etching is stopped at the second gate insulating film 5. After that, as illustrated in FIG. 7(c), the gate side wall 7 is formed on the surface of the gate conductor 6 by thermal oxidation. Furthermore, ions are implanted using the gate conductor and the gate side wall 7 as masks to form the impurity diffusion layer 9 functioning as a source and a drain region. As illustrated in FIG. 7(d), an insulating film is deposited and etched back to form the side wall 8. Finally, the exposed second gate insulating film 5, charge accumulation layer 4 and first gate insulating film 3 are removed by etching using the gate conductor 6 and the side wall 8 as masks.
The second conventional example can solve the problems with the first conventional example. FIG. 8 is an enlarged view illustrating the vicinity of the drain region of the second conventional example. For the present conventional example, the charge accumulation layer 4 extends outside the gate side wall 7, so that the electrons in the distribution 11 of injected CHEs are effectively accumulated in the charge accumulation layer 4 to improve efficiency in writing the injected CHEs. Furthermore, dry etching does not damage the laminate insulating film (3 to 5) at the gate end to prevent accumulated charges from leaking into the substrate and electrodes. Patent Document 1: Japanese Patent Laid Open Publication No. 2003-60096